Silicon integrated circuits that have been produced in recent years generally have so called multilayered wiring structures.
FIG. 3 is a cross sectional view of a known embodiment of an MOS silicon integrated circuit having a multilayered structure. The arrangement illustrated in this figure is a portion of a static RAM.
The elements of the structure of FIG. 3 include a silicon substrate 51, a field insulation layer 52 of a LOCOS structure, a gate insulation layer 53, a gate electrode 54, a source 56, a drain 57, a first interlayer insulation layer 58 and a second interlayer insulation layer 60. In addition, the structure includes a polysilicon layer 59 that comprises a first wiring layer having a high resistance region formed in a portion thereof to constitute a high resistance load for the static RAM. The aluminum layers 61a, 61b and 61c form a second wiring layer. The aluminum layers 61b and 61c are connected to the gate electrode 54 and the source 56 via openings formed in the first interlayer insulation layer 58 and the second interlayer insulation layer 60, respectively. The aluminum layer 61a is connected to the polysilicon layer 59 via the opening formed in the second interlayer insulation layer 60.
In the above described arrangement, the opening for the connection of the gate electrode 54 and the opening for the connection of the source 56 are formed in the same step. For this purpose, the opening for the connection of the polysilicon layer 59 can be formed by etching only the second interlayer insulation layer 60, but the first interlayer insulation layer has to be etched further in order to form the opening for the connection of the gate electrode 54 and the opening for the connection of the source 56. Accordingly, the polysilicon layer 59 is exposed to an etchant in the opening for the connection of the polysilicon layer 59, for a long period of time even after the completion of the etching for the second interlayer insulation layer 60. Therefore, a problem arises that etching is effected as far as the polysilicon layer 59, which should not be etched, resulting in conduction failure of the device.